1. Field of the Invention
The invention is related to the field of circuit simulations, and in particular, to a technique for efficiently and accurately simulating memory arrays in SPICE.
2. Related Art
SPICE (Simulation Program with Integrated Circuits Emphasis) is a simulator for electronic circuits. The use of SPICE simulation beneficially allows circuits to be tested and analyzed without actually requiring that such circuits be physically constructed.
FIG. 1 depicts a conventional methodology for analyzing a circuit using SPICE simulation. An electronic circuit is typically defined initially as a “netlist”, which is simply a listing of devices and the connections between those devices. Typically the “devices” will be individual electronic components, such as transistors, resistors, and capacitors. However, depending on how the circuit is defined, the devices in a netlist may be basic functional blocks, such as AND gates and OR gates.
In any case, to begin a SPICE simulation, a netlist is separated into its component elements and interconnects in a “PARSE NETLIST” step 110. Mathematical models for those component elements are then specified in a “MODEL GENERATION” step 120. Specifically, the elements and interconnects extracted from the netlist in step 110 are defined as black box elements and interconnections between terminals of those black box elements. The internal behavior of each black box element is specified by a set of model equations that simulate the internal behavior of the device the black box element represents. The set of model equations generate voltage and/or current values for certain terminals of the black box element based on voltage and/or current values (and optionally historical voltage and/or current values) at other terminals of the black box element. Therefore, the set of model equations for a given black box element can be considered to be functions of state variables that represent the voltage, current (and optionally the historical voltage/current) values at the terminals of that black box element.
The combined model equations for the entire circuit are then solved in a “SPICE ANALYSIS” step 130. Specifically, a SPICE engine (i.e., an equation solver based on the SPICE algorithms) determines a set of voltages for the model element terminals that satisfies all the model equations and provides a net zero total current within the circuit (i.e., a set of voltages that results in Kirchoff's Laws being satisfied for the circuit). This equation solving operation is performed over a series of time steps across a range of inputs (sometimes referred to as the “input vector” for the simulation), thereby generating voltage/current results over time that are presented as the behavior of the circuit in an “OUTPUT” step 140.
In this manner, SPICE simulation provides a means for accurately determining the behavior of a circuit design. However, increases in circuit complexity and/or vector length can result in superlinear increases in computing time and memory usage for a SPICE engine. Specifically, because the circuit is “flattened” in step 120 (i.e., model elements (equations) are generated for every element defined in the original netlist), increases in circuit size and/or vector length will require a disproportionately larger increase in computing time and/or memory requirements.
Therefore, modern circuits are often analyzed using SPICE simulation techniques that are sometimes referred to as “fast-SPICE”, in which intelligent approximations are used to reduce the computational load on the SPICE engine. Some conventional fast-SPICE techniques include dividing a large circuit into smaller sub-circuits (i.e., static or dynamic “partitioning”), or performing pre-analysis of the circuit design to determine which portions of the circuit will actually be operational so that analysis can be performed on only those portions of the circuit (i.e., “array reduction” or pattern detection).
Unfortunately, conventional fast-SPICE techniques are unable to effectively deal with large memory arrays when a large percentage of the cells are accessed. These large arrays are typically present in most modern IC designs. For example, a memory array structure precludes the efficient use of partitioning techniques, because the interconnected repetitive construction of the array precludes division into substantially independent sub-groupings. Likewise, array reduction techniques may provide some reduction in memory usage and runtime for relatively short input vectors by limiting analysis to a few cells in a memory array that are accessed over the course of the simulation. However, for the longer input vectors required to fully test modern circuits, the benefits of array reduction are quickly eliminated.
Accordingly, it is desirable to provide an efficient and accurate system and method for performing SPICE simulations on memory arrays.